| |
A3P030 |
A3P060 |
A3P125 |
A3P250 |
A3P400 |
A3P600 |
A3P1000 |
 |
A3PE600 |
A3PE1500 |
A3PE3000 |
| ARM-Enabled ProASIC3/E Devices |
CoreMP7 |
|
|
|
|
|
|
M7A3P1000 |
|
|
|
| Cortex-M1 |
|
|
|
M1A3P250 |
|
M1A3P600 |
M1A3P1000 |
|
M1A3PE1500 |
M1A3PE3000 |
| System
Gates |
30 k |
60 k |
125 k |
250 k |
400 k |
600 k |
1 M |
600 k |
1.5 M |
3 M |
VersaTiles
(D-Flip-Flop) |
768 |
1,536 |
3,072 |
6,144 |
9,216 |
13,824 |
24,576 |
13,824 |
38,400 |
75,264 |
RAM
kbits
(1,024 bits) |
- |
18 |
36 |
36 |
54 |
108 |
144 |
108 |
270 |
504 |
| 4,608-Bit
Blocks |
- |
4 |
8 |
8 |
12 |
24 |
32 |
24 |
60 |
112 |
FlashROM
(FROM)
bits |
1 k |
1 k |
1 k |
1 k |
1 k |
1 k |
1 k |
1 k |
1 k |
1 k |
Secure
(AES) ISP 1 |
No |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
| PLLs |
- |
1 |
1 |
1 |
1 |
1 |
1 |
6 |
6 |
6 |
| VersaNet
Globals |
6 |
18 |
18 |
18 |
18 |
18 |
18 |
18 |
18 |
18 |
| I/O
Standards |
Std. &
Hot Swap |
Std.+ |
Std.+ |
Std.+/
LVDS |
Std.+/
LVDS |
Std.+/
LVDS |
Std.+/
LVDS |
Pro |
Pro |
Pro |
I/O
Banks
(+JTAG) |
2 |
2 |
2 |
4 |
4 |
4 |
4 |
8 |
8 |
8 |
| Single-Ended I/O / Differential I/O
Pairs* |
QN132
|
81 |
80 |
84 |
87/192 |
|
|
|
 |
|
|
|
VQ100
|
79 |
71 |
71 |
68/13 |
|
|
|
|
|
|
FG144
|
|
96 |
97 |
97/24 |
97/25 |
97/24 |
97/25 |
|
|
|
TQ144
|
|
91 |
100 |
|
|
|
|
|
|
|
PQ208
|
|
|
133 |
151/34 |
151/34 |
154/35 |
154/35 |
147/65 |
147/65 |
147/65 |
FG256
|
|
|
|
157/38 2 |
178/38 |
179/45 |
177/44 |
165/79 |
|
|
FG484
|
|
|
|
|
194/38 |
227/56 |
300/74 |
270/135 |
280/136 |
280/136 |
FG676
|
|
|
|
|
|
|
|
|
439/209 |
|
FG896
|
|
|
|
|
|
|
|
|
|
616/300 |
* 高级信息可以更改
1 带ARM的ProASIC3器件不支持AES;
2 M1A3P250器件不支持该封装;
3 带M7、M1前缀系列是在原ProASIC3/E的基础上增加了可嵌入的ARM软核,当未嵌入ARM时两者使用上没有区别。 |